module top (input clk,
            input res_n,
            input a,
            output reg b);
    reg res_r;
    reg res_r_r;
    
    always @(posedge clk or negedge res_r_r)
    begin
        if (!res_r_r)
            b <= 1'b0;
        else
            b <= a;
    end
    
    always @(posedge clk or negedge res_n)
    begin
        if (!res_n)
            {res_r,res_r_r} <= 2'b00;
        else
            {res_r_r,res_r} <= {res_r,res_n};
    end
    
    
endmodule
